歐盟(E.U.)最近啟動一項為期三年的「為下一代高性能CMOS SoC技術整合III-V族奈米半導體」(INSIGHT)研發計劃,這項研發經費高達470萬美元的計劃重點是在標準的互補金屬氧化物半導體(CMOS)上整合III-V族電晶體通道。最終目的則在於符合未來的5G規格,以及瞄準頻寬更廣、影像解析度更高的雷達系統。

除了IBM (瑞士),該計劃將由德國弗勞恩霍夫應用固態物理研究所Fraunhofer IAF、法國LETI、瑞典隆德大學(Lund University)、英國格拉斯哥大學(University of Glasgow)以及愛爾蘭丁鐸爾國家研究所(Tyndall National Institute)等組織聯手進行。

![20160308_EU_NT01P1](//images.eettaiwan.com/15mr7p4rjmth/3SYeDv0yXSEuSkcUImukQS/597e742ead8154b0f16b87e64ebb5bc2/20160308_EU_NT01P1.jpg)
採用IBM模板輔助選擇性外延(TASE)技術製造的單晶結構圖——矽晶部份是綠色,III-V族半導體以紅色表示
(來源:IBM)

There will be two phases to the program led by IBM and Lund University, with IBM concentrating on prototyping conventional planar transistors with III-V channels, whereas Lund University will investigate the feasibility of vertical III-V transistor channels.

[Learn to implement crypto-security on bare-metal ARM Cortex-M processors at ESC Boston] "First the partners will decide together whether the horizontal or vertical transistor prototypes are the most promising," IBM scientist Lukas Czornomaz told EE Times in an exclusive interview. "Then we will work together to deliver an RF [radio frequency] test circuit, such as a PA [power amplifier] by the end of the three-year program."

IBM is confident that its planar method will work, because it has already demonstrated its feasibility at below 14 nanometer in a paper last year titled IBM Scientists Present III-V Epitaxy and Integration to Go Below 14nm.

The way IBM's process works is by what they call "template-assisted selective epitaxy." They grow an oxide wire where they want the III-V transistor channel to eventually be for a gate-first CMOS-compatible III-V FinFETs on silicon substrates. Next they coat the nanowire with the III-V material so that it only touches the substrate in just a nanoscale or even angstrom-scale area. Lastly, they removed the oxide from inside the III-V coated nanowire, thus resulting in a III-V nanotube transistor channel in precisely the correct position.

![20160308_EU_NT01P2](//images.eettaiwan.com/15mr7p4rjmth/6vAftOIvhSGmYUCo60CKs8/bd6fd8370ad995b70714e4c9edd64060/20160308_EU_NT01P2.jpg)
(a)採用IBM技術整合於矽晶上的III-V族半導體橫截面圖。由堆疊斷層組成的晶種區(b,c)存在較多缺陷,而遠離晶種區域可觀察到完美晶格結構——未與矽晶匹配的部份僅8% ,呈現完全鬆弛的III-V結構(d,e)
(來源:IBM)

IBM predicts millimeter-wave RF performance at a much lower power consumption level than today, facilitating not just 5G but also cognitive computers, next-generation Internet of Thing (IoT) and the cloud-based platforms supporting them.

Insight's stated goals are to scale CMOS beyond the seven-nanometer node thereby opening up a whole new range of applications serviced by ultra-high-performance systems on chip (SoCs). The other partners, Fraunhofer, Fraunhofe, LETI, Lund University, University of Glasgow and the Tyndall National Institute also all have III-V on CMOS expertise which they will bring to bear on the project.

Insight is funded under the E.U.'s Horizon 2020 Program for Research and Development (grant number 688784).

編譯:Susan Hong

(參考原文:E.U. Tackles III-V on CMOS,by R. Colin Johnson)