DAC 2022重回實體 現場聆聽最新電子設計趨勢 !

電子設計領域的年度盛事--Design Automation Conference (DAC)終於在2022年恢復實體會議,EE Times歐洲特派記者、embedded.com主編Nitin Dahad從倫敦飛往舊金山,與現場多家重量級EDA供應商與IC設計領域專業人士,共同探討了雲端EDA、智慧系統設計、晶片驗證等技術最新趨勢,還有數位分身、元宇宙等當紅應用...

時長: 31:23 | 發佈者: EE Times Taiwan | 發佈時間: 2022-07-28

DAC 2022重回實體 現場聆聽最新電子設計趨勢 !

HOST: Welcome to embedded Edge with Nitin, a podcast that brings to life the stories behind today’s embedded systems, technologies, and products. It’s the show where you’ll hear from both engineers and executives on some of the most topical news and most pressing challenges in the world of embedded system design. Here’s your host, editor-in-chief of embedded.com, Nitin Dahad.

NITIN DAHAD: Hello, welcome to the latest episode of embedded edge with Nitin. We’ve just returned from the 59th Design Automation Conference in San Francisco, very much a return to normal, live, in-person event.

The conference keynotes were given by Mark Papermaster of AMD, Anirudh Devgan of Cadence, and Steve Teig of Perceive. Their focus respectively was on advancing EDA through the power of AI and high-performance computing, computational software and the future of intelligent electronic system design, and machine learning for real: why principles, efficiency, and ubiquity matter.

Papermaster set the scene and something we’ve become accustomed to hearing – about the challenges posed by die size limitations, power and performance, transistor efficiency, and cost and productivity. All require design as well as design automation.

He chose to focus on the need for more ecosystem partnerships and collaboration to push beyond the limitations posed by these challenges. In his words, he said, “We must collaborate as an industry, we have to have a shared vision of the problems we have to solve, and we need a common view of the challenges.” He went on to talk about the use of high-performance computing, or HPC, needed to generate next generation devices, and how design technology co-optimization, or DTCO, is the only way we are going to realize the complexity of new process nodes. Chiplets, he noted, will play an increasingly important role in enabling the next generation of devices.

The conference featured a show floor too, and here we took the opportunity to catch up with the major EDA companies as well as a number of companies involved in enabling design and design automation – from design to verification, IP building blocks (including connectivity), eFPGA, and of course security.

This is the first of two episodes from DAC 2022. In this episode, I spoke to Siemens EDA, Synopsys, Cadence, Brekker, and eFabless. In second episode, you’ll hear from PQShield, Flex Logix, proteanTecs, Arteris, Menta, and Alphawave.

So let’s get this episode started with two interviews with Siemens EDA.

I’m here with Ravi Subramanian, the senior vice president of Siemens EDA. Hi Ravi.

RAVI SUBRAMANIAN: Hello, Nitin. Glad to be here.

NITIN DAHAD: So, what’s your focus here at DAC?

RAVI SUBRAMANIAN: First and foremost, we’re back. We’re back in person, and it’s really great to see the EDA community that is a community of software developers, our customers who are either systems or semiconductor companies developing next generation chips from automotive to data center to IoT, to even pharma chips.

NITIN DAHAD: We talked a little earlier, and you talked about tectonic shifts in the industry. Just highlight some of those please.

RAVI SUBRAMANIAN: Sure. There are three tectonic shifts really to take note. First and foremost is, we’re coming on what people say is the end of Moore’s Law, but Moore’s Law continues not to end. And we’re also seeing now, we’re in the first decade of what we call more than more than Moore. And in this first decade, we’re also seeing that 3D-IC has come to bear. What this means is, the scale of system complexity that can be captured within a package is astounding today. And that tectonic shift means the possibilities of how much system complexity can be captured within traditional integrated circuit technology is growing leaps and bounds. A second tectonic shift has to do with the fact that more and more systems companies are doing more electronics and semiconductor R&D. This means we are going to see growth of the EDA business being driven by much more than classical semiconductor companies, but overall technology spending on electronics and semiconductor. And finally, the third is that AI and software are enabling customers to create huge value in their businesses. What that means is, the product platforms that customers are building now are very centered on software driven value and enabling AI to get faster insights. That’s changing the nature of what chips customers are building, and how they’re connecting these chips with other parts of the system.

NITIN DAHAD: Now one of the things I think with the Siemens acquisition of Mentor, and I think you showed me how the transition of factory automation has evolved into simulation environments, the digital twin, and that digital twin leads to the metaverse. Can you just tell us a little bit about providing that door to various sort of digital twin environments?

RAVI SUBRAMANIAN: Sure. Today, the way that digital twin has evolved is to really create a virtual model of a object in the physical world, whether it’s a propeller or a jet foil or a food and beverage container or a component in a car. That technology that’s enabled the creation of the virtual world is now enabling the creation of a virtual world where it’s going beyond the component to the environment the component sits in. And the first stage of that has been creating what is called a digital twin, which is a representation not just of the product but the environment and the system in which that product sits. And that enables the creation of, for example, a digital twin of a factory, which is how Siemens pioneered the idea of the digital twin. You can have a digital twin of a complete manufacturing facility before it is even built. You can understand how components selected to create that factory will perform as the factory’s operating. You can even have software that’s running on industrial PCs in that factory showing how the factory will perform. That has been critical in enabling training of people to new factories. So it’s becoming the door to getting educated into a new environment, and ultimately, what has the new universe opened by new technology in that environment. So you can think of digital twins as a doorway to the metaverse, and you can also think of every industry will evolve its own metaverse. And hence that evolution of digital twin in the metaverse.

NITIN DAHAD: That’s fascinating. And I think that was part of the recent announcement with Nvidia.

RAVI SUBRAMANIAN: Indeed. So Siemens and Nvidia made a joint announcement last week about the bringing together of two worlds, and that is the world of the digital twin, which Siemens has pioneered, and then the world of photorealistic 3D rendering of the digital twin to create a truly realistic picture of the environment in the metaverse, so much so that with the digital twin created by Siemens and the metaverse enhanced through 3D photorealism through Nvidia’s chip technologies and semiconductor innovation, we’re able to create an environment which is so real that it almost is another world, but also the world in which people can be trained on new equipment, people can learn about how new suppliers can deliver equipment into their markets, and people can actually train people in remote areas to develop new capabilities. And ultimately, while it is another world, it is going to make our world much, much smaller.

NITIN DAHAD: Yes, and I did see that at Nvidia last week when I visited them, they showed me some really amazing things. Ravi, thank you very much.

RAVI SUBRAMANIAN: Thank you, Nitin. It’s a pleasure.

NITIN DAHAD: I’m with Sumit Vishwakarma, a product manager with Siemens EDA. Sumit, hello.

SUMIT VISHWAKARMA: Hello, Nitin. How are you?

NITIN DAHAD: I’m good. Okay, so you had a big launch at DAC, Symphony Pro. What’s that all about, and why did you need it?

SUMIT VISHWAKARMA: Absolutely, Nitin. Symphony Pro is the advanced tier of Symphony, a mixed-signal product from Siemens EDA. And we launched Symphony four years back in 2018. And since then, we realized that the whole mixed signal verification is evolving. And to address these new challenges in the verification methodologies for mixed signal, we realized that we need to come up with a new engine, and hence Symphony Pro was launched to address those challenges.

NITIN DAHAD: Now that comes up with a few things, like real number modeling and power awareness and things like that. Can you tell us a little bit about what that does to help with mixed signal verification?

SUMIT VISHWAKARMA: Absolutely. So as you know, the designs, they are evolving, especially on the mixed signal side, and there’s more analog contents coming up in SoCs. And for that reason, what is happening is, if you try to simulate everything in analog it’s going to be a very slow simulation. So for that, the methodologies are evolving, and real numbers are used to replace the analog blocks. And for that to happen, there needs to be a proper methodology which should be used for verifying these real number models, and there is the Xcelerator initiative for bringing standards in the model such as user defined net types standards. So there’s definitely need for simulators to support these new standards. So that’s definitely one thing. The second area where we definitely felt the need is in mixed signal debugging is very critical. And most of the mixed signal bugs happen at the A to D boundaries, and they are hidden deep in the hierarchy. So we definitely felt that engineers spent a significant of time in debugging these bugs, which are very cumbersome and time consuming. So we wanted to address that, and hence we came up with a very innovative debug solution, Symphony Pro.

NITIN DAHAD: How are companies using this?

SUMIT VISHWAKARMA: Yes, absolutely. So what we have seen is, specifically in system level companies, the companies which are doing SoCs, their whole, most of their verification methodology is digital based. And the moment when the DUT [device under test] is no longer just a pure digital chip and when it becomes a mixed signal chip, you can no longer use the same verification infrastructure. And so you need to come up with different methodologies to model analog contents in your chip so that you can reuse the same infrastructure. And for that reason, we have seen requests coming in from our customers that our simulators should be able to support these new standards which they are trying to deploy in their flows.

NITIN DAHAD: And you’ve had some customers who are already using this now.

SUMIT VISHWAKARMA: Absolutely. So we are very happy that some of our key customers such as STMicroelectronics has been using Symphony Pro, and they have seen significant value, specifically in their advanced configurations, such as multi-layer designs, where they have analog instantiating digital and so on and so forth. And the other customer is Silicon Labs. That’s a company, IoT company based in Austin, in Texas, and they have also seen great productivity improvement with Symphony Pro. And we are very happy that both our customers have endorsed us.

NITIN DAHAD: Sumit, thank you very much.

SUMIT VISHWAKARMA: I appreciate it. Thanks, Nitin. Great time.

NITIN DAHAD: I’m now with Sandeep Mehndiratta, VP of cloud at Synopsys. Sandeep, hello.


NITIN DAHAD: So you did a tech talk here today, tell me what were the key things, takeaways that people who attended would have got from that?

SANDEEP MEHNDIRATTA: The tech talk was titled, “It’s Cloudy Out There,” and it was sharing the experiences and learnings we at Synopsys have had over the last 18 months or so developing a cloud solution, why people are moving to cloud, what’s preventing them to move to cloud, and what’s enabling them, and how Synopsys is accelerating that transition of doing chip design on public cloud.

NITIN DAHAD: So what are the key macrotrends you identified?

SANDEEP MEHNDIRATTA: The key macrotrends we talked about today were around how software is driving differentiation in technology today, how chips are enabling that transition. So as an example, if you have, if you look at various applications with AI/ML technologies, whether they be around enabling self-driving cars or how research is done in pharmaceuticals and vaccines, or even, you know, advanced gaming using AI techniques, the software is AI and ML based, powered by purpose built AI microprocessors that have low latency and high speed, delivering the necessary performance to realize those applications.

NITIN DAHAD: Recently you announced the cloud EDA, pay as you go EDA service. But I think you made an announcement here about something around various sort of targeting instances. Tell me a little about that.

SANDEEP MEHNDIRATTA: Sure. Good question, Nitin. About end of March, we announced the industry’s first software as a service solution for chip design in a partnership with Microsoft, and that was our SaaS doray. Today, we rolled out the next evolution of that with the concept of instances, and we announced three instances built around customer personas, an analog instance for analog designers, a digital instance for digital designers, and a verification instance for verification engineers. And what we’ve done with these instances is brought together curated flows, end to end flows for analog design through schematic verification, layout, physical sign-off, and similarly for digital and verification, where we have stitched together the tools, typically what a CAD team would do for their design teams. We have optimized these flows through available pre-qualified compute, and enabled them in a SaaS environment accessible through a browser for small companies to come in, get started on doing design, go from a concept to prototype in a matter of hours, versus days, weeks, or months.

NITIN DAHAD: And why did you do that? Did you see that customers are looking for that, or was it something you planned all along?

SANDEEP MEHNDIRATTA: We think that cloud provides a platform to democratize design. And we did this looking at customer demand, because as customers are moving to cloud, setting up complex EDA flows is a heavy undertaking from a resource and time point of view. So we saw this opportunity. We were looking at customer feedback, and what we have done is, these jump-start flows, or instances, as we call them, give customers the ability to get started quickly and build on as their expertise and design knowledge develops.

NITIN DAHAD: Okay, one last question. So you launched in March. What are your key learnings so far?

SANDEEP MEHNDIRATTA: So a few key learnings. One, cloud is not a ‘lift and shift’ model. Customers need help in migrating their current flows to cloud. Part of our instance rollout is from that learning. Second is how do you make it easier for customers to buy, use, and deploy cloud is an area we are focusing on, because it’s important for customers to be able to access, experiment, and then deploy in production. So ease of adoption is a key learning that we are focusing on.

NITIN DAHAD: Sandeep, thank you very much.

SANDEEP MEHNDIRATTA: Nitin, thank you very much.

NITIN DAHAD: I’m now here with Dave Kelf, CEO of Breker Verification Systems. Dave, hello.

DAVE KELF: Hi Nitin. Good to be here.

NITIN DAHAD: Tell me a little bit about Breker.

DAVE KELF: Certainly. So Breker is in the business of test suite synthesis. We generate test content for various environments, including UVM block based simulation, SoC environments, post silicon environments for semiconductors, of course, and within the SoC environment we have a number of applications, which are like pre-cast scenario tests for things like cache coherency, security testing, that kind of thing. And in the UVM space, we generate block based tests that fit within the UVM test bench, the existing UVM test bench. And what we do is generate sequence sets in the virtual environments on top of that.

NITIN DAHAD: And you work with all the processors, Intel, Arm, RISC-V. Tell me a little bit about what you’re doing with all of those and some of the trends.

DAVE KELF: Yes, certainly. So yeah, it’s interesting. When you mention the trends, of course, RISC-V is becoming much more important these days. We’ve seen a big increase in interest in the usage of that. Arm is the solid, stable environment, and then Intel of course, you have the server environments and what have you. I would say that, you know, we work with all three of these environments, and what we’re doing is providing at the SoC level various test environments that provides tests for SoCs that use all these processors. So for example, in cache coherency, as we see more advanced processors that use multi-level cache environments, coherent fabrics, coherent IO, and so on, it’s important to provide a test environment that thoroughly brings out, you know, these complex SoCs. So we provide pre-cast verification IP type tests for this, and we’re working with a number of different companies using all those processors, and it’s a very effective way to do a thorough coherency test of these SoCs before they go to fabrication, and actually post fabrication as well.

NITIN DAHAD: And you’ve grown quite significantly in the last three years, you told me.

DAVE KELF: That’s right. So the company has been running now for a number of years, started as a services company, built this test suite synthesis technology together with some operating system technology underneath. And in the last three years we’ve really seen our business take off. Out of the pandemic now, a lot of companies are actually building more advanced SoCs. As we mentioned, the advent of RISC-V and now RISC-V really becoming more commercially viable, and some of these other technologies coming to the forefront have really propelled that business in a big way.

NITIN DAHAD: This week you announced at DAC a relationship with Codasip, and this is not just a one off. You’ve done announcements with Imperas and joined RISC-V International. What’s it all about?

DAVE KELF: So yes. RISC-V is an interesting technology. It’s been worked on for quite a few years now, and we’re seeing it at the point where the RISC-V instruction set is being used for more and more advanced processors. So it’s entering the application processor world. To do that, the kind of verification that needs to be applied to those processors has to really be commercial grade. You can’t get away with, you know, just straightforward IP block verification. There’s a lot of capability that needs to be wrung out inside these different processors. We know that Arm for many years has invested many millions of dollars per year in their verification environments, and it’s going to be important for RISC-V to be successful for them to do the same things, for these companies to do that. To make that happen, and to make sure that different vendors can all provide RISC-V processors that all work together and are compatible, special organizations and flows and metrics are going to have to be created, I think, which provides that kind of commercial grade verification that’s required. So Codasip, fascinating company doing a really good job in this space, I believe, and they’re very, very focused on really solid, rigorous verification, and the quality of their processors. And as they step up and produce and more and more powerful processors, they’re looking at ways that they can get that Arm level kind of quality in their devices. So they’re collaborating with different companies, and the announcement we made with them is a collaboration on this SoC integration verification, areas such as cache coherency, security, and other items, which match the apps that we just mentioned. You know, this is something that we’re working with Codasip on how to sort of build this out and really make this powerful, not just for Codasip’s RISC-V IP, but potential generally across the industry. And similarly, we did an announcement with Imperas. We’re working with them on some of their interfaces and other technologies, and we joined RISC-V International itself as well.

NITIN DAHAD: What do you see as the future in terms of what you’re doing with that? Has it informed some other ways of working with RISC-V and verification?

DAVE KELF: Yes, it’s a great question. And you know, it’s early days yet. Right now it’s a collaboration between the different companies. But potentially, we could see an organization form which really focuses on this commercial grade level verification and opens or provides to the industry at large either metrics or methodologies or mechanisms to really allow these different RISC-V processor developments to be verified at a level that are acceptable to the kind of large organizations that really want to make use of them for full application processors similar to what they use Arm for today.

NITIN DAHAD: Well Dave, thank you very much.

DAVE KELF: Yes, thank you, Nitin. It’s good to meet you.

NITIN DAHAD: I’m now with Frank Schirrmeister, group director for solutions and ecosystems at Cadence. Frank, hello.

FRANK SCHIRRMEISTER: Thanks for having me. Nice meeting you.

NITIN DAHAD: What are the key trends that are driving some of the things you’re showing here at DAC?

FRANK SCHIRRMEISTER: So I think the overarching trend, if you start from a consumer perspective, is really what you would refer to as the hyperconnectivity from the sensors that touch us in day-to-day life and touch the industrial domain, the automotive domain, through what we refer to as edge computing through the networks. We are at 5G. Today we talk about 6G going forward, into the data center, you have all the compute happening, to create insights. And there’s I guess balancing right now going on where which compute is happening. Is it, what’s happening in the data center? What’s happening at the various edges. So that’s really the overarching driver, and that hyperconnectivity then can be seen in items we show here at DAC, like we gave an automotive overview where your car data, terabytes of data created in very short amounts of times, is transmitted, analyzed, creating insights about things like usage of parts in your car. That’s all computed in the data center and transmitted through networks, not even taking into account things like autonomy for cars in there. So those are the overarching trends driving a lot of our products. And then from here, as Cadence and as EDA in general, but Cadence specifically, will provide to you capabilities around the building blocks for the semiconductors. That’s our IP domain. The verification, that’s where you have our dynamic duo of emulation and prototyping where you have AI enabled verification with Xcelium ML to make sure that things are functionally correct, that they are safe, that they are secure. Through AI enabled digital implementation, that’s where our Cerebrus technology comes in to optimize PPA (performance, power, and area) for large digital implementations. Through customer implementation, where you have all the RF, the analog mixed signal simulation, and then extending into the system domain where it’s all about electromagnetic analysis, thermal analysis, extending into computational fluid dynamics.

So those consumer requirements, making our world so hyperconnected and much more comfortable for us, so to speak, are driving a lot of the requirements. And then you need to take into account things like sustainability. That was a big topic here at Cadence, at Cadence at at DAC, talking about how we can optimize power. We had panels here on discussing sustainability, optimizing carbon emissions in automotive and data centers and everything from a low power perspective. So yes, very exciting trends coming from the hyperconnected world all the way down into the EDA design tools.

NITIN DAHAD: Frank, thank you very much.

FRANK SCHIRRMEISTER: Thanks for having me.

NITIN DAHAD: I’m now with Mohamed Kassem, co-founder and CTO of Efabless Corporation. Mohamed, hello.

MOHAMED KASSEM: Hi. Thank you so much for having me here.

NITIN DAHAD: We’ve just participated in a panel at DAC on democratization of silicon. Tell us a little bit about what you think that means, and where this fits with what you’re doing.

MOHAMED KASSEM: So one of the examples I use for democratization is the travel industry. Before the invention or the presence of a 747 jumbo carrier, the price per seat was too expensive for the average family to travel. When that happened, all of a sudden the price per seat went down, allowed so many more people to be able to do that. And that’s exactly what we do for the chips. We create a platform that makes the cost per chip go down, and also find the knowledge, the attached knowledge to enable the designer to do what they need to do to be in that chip.

NITIN DAHAD: Okay, so like let’s just take us through a customer journey with how they work with Efabless.

MOHAMED KASSEM: So actually, so one of the, a way to simplify building a chip is that we build most of the chip that usually requires knowledge out in multiple domains. We’re able to build the chip with the frame and the packaging. And most people that we found is that if we built this thing, a chip, it has a square area of 10 millimeters squared. That’s an example just, and then provide resources on the chip like power management and interfaces, but leave an area and say, okay, you put my chip here, my block here. So we give them that as a starting point. So the knowledge required to be able to do your own chip, just, it gets minimized. So that’s one. The second part is that when, because we standardize it, I can actually give you a board, because I know the standard board and the standard input and output of IOs of the chip, and even comes with the softwares. When I do that, I can actually take it a little to younger generations, not only the engineers. On a typical customer, let’s call it a startup, for example, they come in and they say, I’m going to use your product, which is a chipIgnite, which is that chip platform, and then I will put my differentiating or technology inside that wide area, and then within four months, I have chips that I can actually use as a minimum viable product. So that is one. On the other hand, from the education perspective, the universities have been one of the biggest customers in general, for courses. They want to actually have practical experience for the students to learn how to design something and put it in a chip and test it and pre-check and close that loop all together.

NITIN DAHAD: And how are you making this little design area easy for them to design components? How are you enabling that?

MOHAMED KASSEM: So the design area, it can be treated as like a socket. So the interface is fixed, and they know what it is. They can actually apply power, their own power supplies, one or two. They apply clocking. They can make it analog IOs or digital IOs. They can treat that box as a socket. But they don’t have to worry about, the thing that are done to make it outside the chip, because ASD and IOs and all this, this is just an environment to have my, internal IP or internal box or CPU, to access the world. So they have to put IO buffers, ASD, in a packet. So they just don’t have to focus on any of that. They just drive, or design for their own. Some of the people did their own accelerators. Some of them have their own new CPUs, RISC-V, and some did like open power CPUs in the empty area.

NITIN DAHAD: So are they using a platform to design that little bit themselves using components from you?

MOHAMED KASSEM: So our platform actually extends. It’s kind of a hybrid, cloud based all the way to the open source EDA. So we have a version of our platform completely set up that you can download and work offline to develop whatever you need analog or digital, and they use that. And then we have, we provide them also with so-called pre-checkers that will give them on the spot feedback to improve or detect any issues in such a way that by the time they’re done, it’s ready to go to the fab.

NITIN DAHAD: Mohamed, thank you very much.

MOHAMED KASSEM: You’re welcome.

NITIN DAHAD: So that brings us to the end of this first episode from the 59th Design Automation Conference. Check out episode two from DAC when I talk to, from PQShield, Flex Logix, proteanTecs, Arteris, Menta, and Alphawave.


That was Embedded Edge with Nitin, and I’m Nitin Dahad. Thanks for listening and see you next time.