《EE Times》主編Brett Brune和《EDN》主編Majeed Ahmad共同導讀分享,讓讀者輕鬆窺見將在EETimes.com發表的首份《Analog Everywhere》特別報導中的一些內容以及類比設計的最新發展...

時長: 19:23 | 發佈者: EE Times Taiwan | 發佈時間: 2023-02-06


ERIC SINGER: You are listening to EE Times On Air, and this is the new EE Times Current. I’m Eric Singer.

ERIC SINGER:您正在收聽的是EE Times On Air,這是最新一集的《EE Times Current》Podcast。我是Eric Singer

ANNOUNCEMENT: For today’s episode we’d like to spotlight, “Elektroda”. Elektroda is where even experts can learn new things in the world of electronics. Engineers from the novice to the Nobel winner swap problems, solutions and discoveries that you won’t find anywhere else. Elektroda – Where Engineers Go for Expertise.


ANNOUNCEMENT: EE Times would like to shout out Microchip. Microchip’s comprehensive Power Management and Analog portfolios support your designs with efficient, low-power, highly integrated, innovative solutions while streamlining your development process and reducing your design risk.  Microchip is…Power and Analog.

ANNOUNCEMENT:EE Times.com想向Microchip致意。Microchip提供全面的電源管理和類比產品組合,以高效、低功耗、高度整合的創新解決方案支援您的設計,同時簡化您的開發流程並降低設計風險。Microchip就是……電源和類比。

ERIC SINGER: Today’s episode highlights a special report from EE Times.com. Here is Brett Brune, Editor-in-Chief of EE Times.com, with Majeed Kamran, Editor-in-Chief of EDN and Planet Analog.

ERIC SINGER:今天這一集重點介紹 EE Times.com 的特別報導單元。現場邀請到《EE Times》主編Brett Brune,以及《EDN》和《Planet Analog》主編 Majeed Kamran。

BRETT BRUNE: Hi, I’m Brett Brune, EIC of EET.com. Joining me today is Majeed Ahmad, EIC of Planet Analog.com. Welcome to the show, Majeed

BRETT BRUNE:大家好,我是 EET.com 的主編Brett Brune。今天和我一起來到這集podcast的是Planet Analog.com 主編Majeed Ahmad。 Majeed,歡迎你的參加。

MAJEED AHMAD: Very glad to be here, Brett

MAJEED AHMAD:Brett,我很高興能來到這裡。

BRETT BRUNE: EET.com is publishing a special report called Analog Everywhere. It will start in mid-January & run thru March. And we are leaning on Majeed and his specialization to make each article a must-read. The report focuses on three main design themes: Sensor interface, R-F solutions, and Power solutions. Majeed, would you please first describe the state of the Analog market—explaining how we arrived at the need to prepare this special report?

BRETT BRUNE:EET.com即將發表一份名為《Analog Everywhere》的特別報導。它將從一月中旬開始,一直持續到三月。我們仰賴Majeed 和他的專業,讓每篇文章都成為必讀文章。這份報導重點關注於三項主要設計主題:感測器介面、射頻(RF)解決方案和電源解決方案。Majeed,請您先描述一下類比市場的狀況——解釋一下我們為什麼需要準備這次的特別報導?

MAJEED AHMAD: Analog design is truly at crossroads. The past decade was mostly spent on cleverly integrating analog building blocks like analog to digital and digital to analog converters, amplifiers, and phase lock loops into system-on-chip – or “SoC” – designs.

MAJEED AHMAD:類比設計確實來到了十字路口。過去十年來,主要著重於巧妙地將類比數位轉換器和數位類比轉換器、放大器和鎖相環等類比建構模組整合到單晶片系統(或“SoC”)設計。

Now, as we are well into the 2020s, three giant markets—Internet of Things, 5G, and Data Centers—promise to revive analog fortunes all over again. Especially, IoT as well as automotive and industrial designs, are all packed with sensors, which are inherently analog devices.

如今,隨著我們進入2020年代,三大市場——物聯網(IoT)、5G和資料中心(Data Center)——可望再次全面重振類比命運。特別是,IoT以及汽車和工業設計都包含了感測器,這些感測器本質上就是類比設元件。

That means analog content is going to increase at a time when standalone analog devices are on the decline in terms of volume shipments due to the integration of analog functional blocks into large, powerful SoCs. In short, analog is still here, and its design clout is likely to grow in the coming years.


BRETT BRUNE: Let’s now focus on a particularly interesting aspect of the report: The Future of analog toolsets in the EDA industry.

BRETT BRUNE:現在讓我們關注在這個報導中特別有趣的方面:EDA產業中類比工具組的未來。

Majeed, can you give us the skinny on this article that I found particularly insightful? (The title is: EDA Tools for Analog: Where Do I Go From Here?)


MAJEED AHMAD: Just as analog IC design is evolving, so, too, are EDA tools, as they evolve to keep up with the demanding verification needs of next-generation chips.

MAJEED AHMAD:正如類比IC設計持續進展一樣,EDA工具也在不斷發展中,因為它們不斷發展,才能滿足下一代晶片嚴苛的驗證需求。

However, while analog, mixed-signal, and RF design tools have continued to grow rapidly and have hit double-digit annual growth rates in recent years, they have not exploded in scope to parallel the range of tools for digital design.


BRETT BRUNE: Who did we interview for this piece?

BRETT BRUNE:我們在這篇文章中採訪了哪些人?

MAJEED AHMAD: Laurie Balch, research director at Pedestal Research, is one source. She provides some backdrop by saying that “The key enabler of digital design automation has been the ability to use abstracted representations of standardized electronic components to synthesize and simulate designs. However, while this is a well-established practice for digital design, it’s far more difficult for analog.”

MAJEED AHMAD:Pedestal Research的研究總監Laurie Balch是消息來源之一。 她提供了一些背景資訊,她說:數位設計自動化的關鍵推手在於能夠使用標準化電子元件的抽象表現,以綜合並模擬設計。然而,對於數位設計來說,雖然這是一種公認的做法,但對於類比來說卻更加困難。

That’s because, by definition, analog operations cannot be represented as just zeros and ones, which permits greater design flexibility but also means greater analysis intricacy.


BRETT BRUNE: What does this add up to, Majeed?

BRETT BRUNE:Majeed,這意味著什麼呢?

MAJEED AHMAD: Well, the EDA industry has not yet successfully developed adequate ways to achieve higher levels of abstraction for analog design techniques, as Balch told us. Here, it’s important to note that there remains a real and perceived mystique surrounding the artistic element of analog design expertise. That’s because analog engineers maintain specialized skills and knowledge to build custom circuitry with minimal standardized components.

MAJEED AHMAD:嗯,正如Balch告訴我們的,EDA產業尚未成功開發出充份可行的方法,以實現類比設計技術所需要的更高抽象級。在這方面,重要的是注意圍繞著類比設計專業知識的藝術成份仍然存在著真實與感知的神秘感。這是因為類比工程師保持其專業的技能和知識,使用最少的標準化元件建構客製電路。

BRETT BRUNE: What’s happening now, as a result?

BRETT BRUNE:那麼,現在發生了什麼變化?

MAJEED AHMAD: Automating all the specialized experience, analysis requirements, and tricks and rules of thumb for making design tradeoffs is neither technically straightforward nor readily welcomed by the design community. Moreover, adopting new analog automation tools, even if they can be optimized for excellent performance, will require engineers to shift their mindset and trust tools that promise to offload more of the manual design tweaking and optimization they’re accustomed to conducting themselves.

MAJEED AHMAD讓所有的專業經驗、分析要求以及設計權衡的技巧和經驗法則完全實現自動化,在技術上既不簡單,也不容易受到設計界的歡迎。此外,採用新的類比自動化工具,即使它們能夠針對出色的性能實現最佳化,也還要求工程師改變其思維並信任這些工具,以減輕其長久以來習慣自己進行的更多手動設計調整和最佳化。

BRETT BRUNE: Who else is quoted in the piece?

BRETT BRUNE:文章中還引用了誰的看法?

MAJEED AHMAD: Sathish Balasubramanian of Siemens EDA. He sees some recognition of the advantages of a top-down digital methodology. For instance, he noted that “There is a paradigm shift underway to adopt digital verification techniques for the functional verification of analog and mixed-signal designs.”

MAJEED AHMAD:Siemens EDA產品、行銷和業務開發主管Sathish Balasubramanian。他看到了人們日益認可由上而下的數位方法之優勢。例如,他指出,採用數位驗證技術,針對類比和混合訊號設計進行功能驗證的典範正在發生轉變。」

Laurie Balch also sees some degree of catching up with digital tools in the future. She expects that, eventually, analog design tools will further mimic the landscape for digital design tools. Especially with the ever-increasing analog content embedded in modern electronic devices, it’s simply not feasible for analog engineers to continue doing so much manual design work.


BRETT BRUNE: OK. But is the industry seeing any progress, Majeed?

BRETT BRUNE:好的。但是,Majeed,這個產業有哪些進展嗎?

MAJEED AHMAD: Yes, there are signs of progress. Take the case of analog simulators, which need to constantly enhance their model parsers to support the latest and greatest process nodes.

MAJEED AHMAD:是的,目前可看到一些進步的跡象。以類比模擬器為例,它必須不斷增強其模型解析器,以支援最新和最強大的製程節點

According to Balasubramanian, this is critical because analog simulators are used to characterize standard cell libraries, which will become foundational digital building blocks for new chips.


He also pointed to the matrix solver, which is the dominant component of the analog simulator, especially for large circuits, and it’s invoked repeatedly during the simulation. Here, new algorithms are being incorporated to improve matrix solving, as well as for parallelization, which can reduce the runtimes in circuit simulators.


BRETT BRUNE: What else will readers discover in this story?

BRETT BRUNE:讀者還可在這則報導中發現什麼?

MAJEED AHMAD: Analog chip developers, people who use these tools, are also expressing a sense of optimism.

MAJEED AHMAD:使用這些工具的類比晶片開發人員也表達了樂觀看法。

When we interviewed Henri Sino, at Analog Devices, he mentioned the lab-quality results for virtual analog designs through EDA tools, which require vast computing power and simulation times. To address this challenge, Analog Devices is prioritizing digitization of go-to-market engineering deliverables — such as datasheets to leverage and thus scale its EDA roadmap.

當我們採訪Analog Devices的Henri Sino時,他提到了透過EDA工具為虛擬類比設計提供實驗室品質的結果,這需要強大的運算能力和模擬時間。為了因應這一挑戰,Analog Devices正優先考慮上市工程交付成果的數位化,例如資料手冊,以利用並擴展其EDA開發藍圖。

Sino added that Analog Devices is also leveraging web-based tools, interactive content, and complete system designs as starting points.

Sino補充說,Analog Devices正利用基於網路的工具、互動式內容和完整的系統設計作為起點。

BRETT BRUNE: Will machine learning matter?

BRETT BRUNE:機器學習重要嗎?

MAJEED AHMAD: Good question because when it comes to key challenges and potential solutions, Laurie Balch has pointed to another vital premise. In the digital design world, increasing design size and complexity using advanced process nodes and materials necessitates more design automation. However, there aren’t enough analog design experts available, and design timelines are too tight for the traditional approaches to continue being sustainable.

MAJEED AHMAD:問得好,因為在談到關鍵挑戰和潛在解決方案時,Laurie Balch指出了另一個重要前提。在數位設計領域,使用先進的製程節點和材料來增加設計規模與複雜度,還需要更多的設計自動化。然而,由於沒有足夠的類比設計專業工具可用,而且設計時間太緊迫,使得傳統方法無以為繼。

As a result, as she anticipates, it’s entirely possible that machine-learning algorithms may be a key to jumpstarting new automation options for analog design methodologies.


BRETT BRUNE: Excellent, Majeed. Let’s also give our listeners a taste of another story they can read in the special report: Analog IPs Automate Integration, Tune to Fab Nodes.

BRETT BRUNE:太好了,Majeed。我們也讓聽眾們體驗這次特別報導中可以閱讀的另一篇文章吧!這則是「類比IP自動化整合,鎖定Fab節點」。

It highlights the collaboration among IP suppliers, foundries, and chip developers for the integration of analog building Blocks.


What’s important to take away from this piece?


MAJEED AHMAD: System-on-chip designs with heterogeneous voltage domains are increasingly moving away from custom analog IP to automated implementation.

MAJEED AHMAD:具有異質電壓域的晶片系統設計,正日益從定客製類比IP轉向自動建置。

Why is that?


MAJEED AHMAD: This way, design engineers don’t have to worry about schedule slips caused by manual analog customizations. It also saves chip designers several months in the design process while making analog circuits less susceptible to on-chip surroundings.

MAJEED AHMAD:這樣一來,設計工程師就不必擔心手動類比客製化導致的進度延誤。它還能在設計過程中為晶片設計人員節省好幾個月的時間,同時讓類比電路不易受晶片環境的影響。

BRETT BRUNE: But automatically-generated analog IP isn’t synonymous with off-the-shelf analog IP, is it?

BRETT BRUNE:但是自動產生的類比IP並不等同於現成可用的類比IP,對嗎?

MAJEED AHMAD: Correct. Rather, analog IP generators bring the previously generated custom-design blocks into the design flow and employ specialized tools to tailor a suitable IP within hours. That, in turn, saves a lot of integration time and effort.

MAJEED AHMAD:沒錯。相反地,類比IP產生器會將之前產生的客製設計模組導入設計流程,並使用專門的工具在數小時內量身打造合適的IP。這因而又能節省了大量的整合時間和精力。

BRETT BRUNE: One of the key challenges semiconductor engineers face when analyzing their solutions, though, revolves around how much analog designs can shrink when moving from one chip manufacturing process node to another. Does the story go into this?

BRETT BRUNE:不過,半導體工程師在分析其解決方案時面臨的主要挑戰之一在於,從一個晶片製程節點轉移到另一個時能讓類比設計縮小多少?在報導中是否提到這部份?

MAJEED AHMAD: : Yes. Another way to think about it is that there are certain analog building blocks that don’t scale adequately to smaller IC manufacturing nodes. Moreover, while digital logic is getting cheaper in modern SoCs, not all analog functions can be incorporated economically.

MAJEED AHMAD:是的。關於這一點的另一種思考方式是,有些特定的類比建構模組無法充份微縮到較小的IC製程節點。再者,雖然現代SoC中的數位邏輯越來越便宜,但並非所有的類比功能都能經濟高效地進行整合。

BRETT BRUNE: And who do we quote in this article?

BRETT BRUNE:我們在這篇文章中引用了誰的話?

MAJEED AHMAD: Ron Lowman at Synopsys is one of the sources in this article.

MAJEED AHMAD:Synopsys的Ron Lowman是本文的主要訪談來源之一。

He narrated how once design engineers start choosing different processes, speed, power consumption, and cost also become key design considerations. Here, it’s worth mentioning that while some analog designs can take advantage of standard CMOS-based manufacturing environments, smaller IoT designs do require special process technologies — which becomes a key factor when designing analog IP.


BRETT BRUNE: What else will readers learn about in this article, Majeed?

BRETT BRUNE:Majeed,讀者還能從這篇文章中了解到什麼?

MAJEED AHMAD: At this technology crossroads, IP suppliers’ closely-knit relationships with semiconductor fabs matter a lot.

MAJEED AHMAD:在這個技術十字路口,IP供應商與半導體晶圓廠之間保持密切關係非常重要。

Take the case of Analog Bits, which was recently acquired by chip design service provider Semifive. It provides fundamental building blocks of high-performance analog. Analog Bits joined the Intel Foundry Services and its IP Alliance program early last year to support the Intel 16-nm process for clocking, sensors, and I/O.

以最近被晶片設計服務供應商Semifive收購的Analog Bits為例。它提供了高性能類比的基本構建塊。Analog Bits去年初加入Intel Foundry Services及其IP聯盟計劃,以支援Intel 16nm製程用於時脈、感測器和I/O

Analog Bits also announced the availability of its IP portfolio for GlobalFoundries’ 12-nm 12LP process node, as well as unveiled plans for analog and mixed-signal IPs catering to TSMC’s 4-nm and 3-nm process nodes.

Analog Bits還宣佈其IP產品組合可用於GlobalFoundries的12-nm 12LP製程節點,以及發佈了針對台積電(TSMC) 4-nm和3-nm製程節點的類比和混合訊號IP計劃。

BRETT BRUNE: Majeed, what are the future challenges of analog IP?

BRETT BRUNE:Majeed,類比IP的未來挑戰是什麼?

MAJEED AHMAD: While transitioning from the highly manual analog design process to the automated generation of code for analog IP blocks saves a lot of time and integration effort, it’s not without challenges, especially when chip foundries continuously move to smaller manufacturing processes.

MAJEED AHMAD:儘管從高度手動的類比設計流程過渡到自動產生類比IP模組的程式碼,節省了大量時間和整合工作,但也並非沒有挑戰,尤其是當晶片代工廠不斷轉向更小的製造製程。

Semiconductor fabs are introducing new process technologies every six months, and these aren’t just scaled-down versions of the previous node; they are increasingly complex and structurally different from the previous node.


BRETT BRUNE: Can you provide an example of this dynamic?

BRETT BRUNE:你能舉例說明這種動態變化嗎?

MAJEED AHMAD: A good example is the new N3 FEIN FLEX technology from TSMC, introduced during the foundry’s 2022 Symposium.

MAJEED AHMAD:台積電在其2022年技術論壇(2022 Symposium)期間推出的N3 FEIN FLEX新技術,就是一個很好的例子。

Transitions to smaller nodes have been seen as a major stumbling block for the analog design realm for quite some time. That makes recent announcements from IP suppliers to support 4-nm and 3-nm process geometries a notable premise. However, when it comes to smaller nodes primarily designed for digital, analog engineers will have to do things differently.

很長一段時間以來,向更小節點的過渡一直被視為類比設計領域的重大障礙。 這使得IP供應商最近宣佈支持4-nm和3-nm製程幾何成為值得注意的先決條件。然而,當涉及主要用於數位設計的較小節點時,類比工程師將被迫採取不同的做法。

BRETT BRUNE: I’ve also heard about the coming transition from FinFET to gate-all-around (GAA) manufacturing process technology in advanced nodes, and that it will bring unique engineering challenges like capacitance compensation. What is involved here?

BRETT BRUNE:我也聽說先進節點中即將從FinFET過渡到「環繞式閘極」(GAA)製程技術,這將帶來電容補償等獨特的工程挑戰。這又牽涉到什麼?

MAJEED AHMAD: It’s a major technology shift, and, as a result, analog integration at these advanced nodes will require much higher levels of mixed-signal circuit innovation.

MAJEED AHMAD:這是一次重大的技術轉折,因此,類比整合採用這些先進節點時將會需要更高度的混合訊號電路創新。

Furthermore, analog and mixed-signal designs on 4-nm and 3-nm nodes will demand a new breed of EDA toolchains to complement the traditional SPICE simulators.


BRETT BRUNE: There is a ton of good information in this and all of the dozen or so articles in this special report.

BRETT BRUNE:這篇文章以及這次特別報導中的十幾篇文章都提供了大量有幫助的資訊。

Many thanks for heading it up, Majeed. And great to see you.


MAJEED AHMAD: You’re most welcome Brett.


ERIC SINGER: That brings the first episode of EE Times Current to its end. Thank you for joining us. Our EE Times Current Shoutout was to MicroChip – Microchip is…Power and Analog. Today’s highlight was Elektroda – Where Engineers Go for Expertise.

ERIC SINGER:時間來到第一集《EE Times Current》的尾聲了。感謝您的收聽。 《EE Times Current Shoutout主要針對MicroChip的……電源和類比領域。今天的亮點是Elektroda——這是工程師尋求專業知識的地方。

EE Times Current is produced by EE Times. The segment producer was Lady Miah Kane. Today’s episode was engineered by Taylor Marvin and Greg McRae from Coupe Studios and Lady Miah Kane. I’m Eric Singer. Thanks for listening.

《EE Times Current《EE Times製作。製作人是Lady Miah Kane。今天這一集podcast由Coupe Studios的Taylor Marvin和Greg McRae以及Lady Miah Kane共同設計。我是Eric Singer。謝謝您的收聽。

參考原文The State of Analog Design in 2023